1. Field of the Invention
The present invention relates to an image sensor and more particularly, to the circuitry of a self-compensating correlated double sampling circuit.
2. Description of the Prior Art
An image sensor is used to transform an optical image signal focused on the sensor into an electrical signal. The image sensor typically consists of an array of light receiving elements where each element produces a signal in response to the light intensity impinging on that element when an image is focused on the array. These signals may then be used to display a corresponding image on a display apparatus, such as a CRT monitor or a LCD display.
Of very well known types of image sensor, one is a charge-coupled device (CCD). Integrated circuit chips containing a CCD image sensor are expensive due to the special manufacturing processes required. Charge Coupled Devices also consumes relatively large power dissipation because of the required clock signals which usually must operate with high voltage.
In contrast to CCD image sensors, CMOS active pixel sensors (hereinafter called APS) have attracted much attention recently because they offer the possibility of monolithic integration of control, drive and signal process circuitry upon a single chip. In addition, they offer: (1) lower voltage operation and low power consumption, (2) process compatibility with on-chip electronics, and (3) potentially lower cost as compared to the conventional CCD because of the wide availability of standard CMOS manufacturing process.
However, it is known that for large area and high density pixel arrays, the analog signal generated by each light receiving element will suffer from varying degrees of parasitic effects, such as those caused by parasitic capacitance, resistance, dark current leakage, or non-uniformity of device characteristics. These parasitic effects are inherent in semiconductor devices and result in degradation of the signal to noise ratio of the image information. Therefore, noise issues pose major challenges which can limit performance of the CMOS APS. These noise sources includes (1) kT/C noise, which is associated with the sampling of the image data, (2) 1/f noise, which is associated with the circuit used to amplify the image signal, and (3) fixed pattern noise (FPN), which is associated with the non-uniformity of the signal processing electronics of the sensor. FPN relating to the columns of an image sensor is visually unpleasant because it is easily detected by the human eye, as it has the effect of vertical lines or strips in the image.
FIG.1 shows the architecture of a conventional image sense amplifier circuit, as described in numerous publications. The column signal is connected to the pixel through a row transistor T1 (the access transistor) and thus is pulled up to a voltage related to the light that has fallen on the pixel. This column voltage level will differ from the actual pixel photosensor voltage (or be xe2x80x9coffsetxe2x80x9d from it) by the gate-source voltage drop of the source follower transistor T2. The resulting voltage level is stored on the capacitor C1 by means of a momentary closure of the switch T4.
In the next phase, the reset transistor T5 in the pixel is turned on, pulling the pixel voltage level up to a reference level. The column voltage is also thereby pulled up to a voltage related to this reference level and offset from it by the gate-source voltage of the source follower transistor T2, as was the case in the first phase. This reference voltage is then stored on the second capacitor C2. Thus, the difference in the voltages stored on capacitors C1 and C2 can be seen to be the pixel photosensor signal. Since the offset voltage due to the source follower transistor as well as the low frequency noise appears as a voltage common to both capacitors, they may be approximately canceled by subtraction. The two signals are transferred to the following stage 8, a differential amplifier which provides for this subtraction through the buffer circuitry 7. However, because these buffer stages 7 have their own offset and noise, a similar reference and subtraction operation is needed, not shown here, which complicates the circuitry further, requiring additional switch transistors and voltage sources.
Moreover, because of the number of devices required to implement this circuitry, there are many sources of variation, which then may result in FPN. In addition, because of the method of cancellation of offset in the subsequent buffer stages, the time required to perform such cancellation will result in reducing the speed of operation.
The present invention is intended to minimize the effects caused by the aforementioned device variations, as well as providing simpler and more compact implementation and higher operating speed.
A signal processor which involves a self-compensating correlated double sampling (CDS) circuit and an ADC for obtaining the signal from a pixel of an image sensor is disclosed. The CDS circuit comprises a first capacitor, a buffer amplifier, and a reference-setting transistor. The first capacitor has a first plate, serving as an input terminal which is charged in response to the pixel photosensor, and the second plate of the first capacitor is connected to a ramp voltage signal when the reference-setting transistor is switched on. This second plate of the first capacitor is also connected to the input terminal of the buffer amplifier. Further, the reference-setting transistor is connected to the second plate of the first capacitor and a ramp voltage supply.
The ADC circuit comprises a second capacitor, a comparator, the buffer amplifier, and the reference-setting transistor. The second capacitor is connected between the buffer amplifier and the comparator, which has a switch transistor being connected between its input terminal and its output terminal. Further, the comparator operates to set a threshold voltage, which is stored on the second capacitor when the switch transistor is on. This operation is commonly referred to as auto-zeroing. Still further, the comparator provides an output signal to a digital counter when the switch transistor is off and the set-reference transistor is switched from off to on so as to receive an increasing ramp voltage.
In the preferred embodiment, the subtraction operation is accomplished immediately at the input to the CDS circuit, so that the subsequent circuitry is simplified. In addition, a simpler interface to the input of the ADC is desirable, again to reduce the complexity of the resulting circuitry, and to increase the speed of operation.